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document # sram142 rev or revised march 2011 p4c1041l low power 256k x 16 (4 meg) static cmos ram features fast access time - 55 ns low power operation single 5v10% power supply 2.0v data retention easy memory expansion using ce and oe inputs fully ttl compatible inputs and outputs advanced cmos technology fast t oe automatic power down when deselected packages C 44-pin 400 mil tsop ii functional block diagram pin config uration tsop ii description the p4c1041l is a 262,144 words by 16 bits high-speed cmos static ram. the cmos memory requires no clocks or refreshing, and has equal access and cycle times. in - puts are fully ttl-compatible. the ram operates from a single 5.0v 10% tolerance power supply. access times of 55 nanoseconds permit greatly enhanced system operating speeds. cmos is utilized to reduce power consumption to a low level. the p4c1041l device provides asynchronous operation with matching access and cycle times. memory locations are specifed on address pins a 0 to a 17 . reading is accom - plished by device selection ( ce ) and output enabling ( oe ) while write enable ( we ) remains high. by presenting the address under these conditions, the data in the addressed memory location is presented on the data input/output pins. the input/output pins stay in the high z state when either ce or oe is high or we is low. the p4c1041l comes in a 44-pin 400 mil tsop ii pack - age.
p4c1041l - low power 256k x 16 static cmos ram page 2 document # sram142 rev or dc electrical characteristics (over recommended operating temperature & supply voltage) (2) sym parameter value unit v cc power supply pin with respect to gnd -0.5 to +7.0 v v term terminal voltage with respect to gnd -0.5 to v cc + 0.5 v t a operating temperature -40 to +85 c t bias temperature under bias -40 to +85 c t stg storage temperature -65 to +150 c i out dc output current 20 ma maximum r atings (1) recommen ded operating conditions grade (2) ambient temp gnd v cc commercial 0c to 70c 0v 5.0v 10% industrial -40c to +85c 0v 5.0v 10% capacita nces (4) (v cc = 5.0v, t a = 25c, f = 1.0mhz) sym parameter conditions typ unit c in input capacitance v in =0v 6 pf c out output capacitance v out =0v 8 pf sym parameter test conditions min max unit v ih input high voltage 2.4 v cc + 0.3 v v il input low voltage -0.2 0.6 v v ol output low voltage (ttl load) i ol = +2 ma, v cc = min 0.4 v v oh output high voltage (ttl load) i oh = -1 ma, v cc = min 2.4 v i li input leakage current v cc = max, v in = gnd to v cc -1 +1 a i lo output leakage current v cc = max, ce = v ih , v out = gnd to v cc -1 +1 a i sb1 standby power supply current (cmos input levels) ce v cc - 0.2v, v cc = max, f = 0, outputs open, v in v cc - 0.2v or v in 0.2v 50 a i cc dynamic operating current cycle time = min, ce = v il , i i/o = 0 ma, other pins at v ih or v il 60 ma i cc1 dynamic operating current (cmos) cycle time = 1 s, ce 0.2v, i i/o = 0 ma, other pins at 0.2v or v cc - 0.2v 10 ma
p4c1041l - low power 256k x 16 static cmos ram page 3 document # sram142 rev or sym parameter -55 unit min max t rc read cycle time 55 ns t aa address access time 55 ns t ac chip enable access time 55 ns t oe output enable access time 30 ns t lz chip enable to output in low-z 10 ns t olz output enable to output in low-z 5 ns t hz chip disable to output in high-z 20 ns t ohz output disable to output in high-z 20 ns t oh output hold from address change 10 ns t be byte access time 55 ns t hzbe byte disable to high-z output 25 ns t lzbe byte enable to low-z output 10 ns ac electrical characteristicsread cycle (v cc = 5v 10%, all temperature ranges) (2)
p4c1041l - low power 256k x 16 static cmos ram page 4 document # sram142 rev or timing waveform of read cycle no. 1 timing waveform of read cycle no. 2 ( oe controlled) (5,6) notes: 1. stresses greater than those listed under maximum r atings may cause permanent damage to the device. this is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specifcation is not implied. exposure to maximum rating conditions for extended periods may affect reliability. 2. extended temperature operation guaranteed with 400 linear feet per minute of air fow. 3. transient inputs with v il and i il not more negative than C2.0v and C100ma, respectively, are permissible for pulse widths up to 20 ns. 4. this parameter is sampled and not 100% tested. 5. we is high for read cycle. 6. ce is low and oe is low for read cycle. 7. address must be valid prior to, or coincident with ce transition low. 8. transition is measured 200 mv from steady state voltage prior to change, with loading as specifed in figure 1. this parameter is sampled and not 100% tested. 9. read cycle time is measured from the last valid address to the frst transitioning address.
p4c1041l - low power 256k x 16 static cmos ram page 5 document # sram142 rev or ac characteristicswrite cycle (v cc = 5v 10%, all temperature ranges) (2) sym parameter -55 unit min max t wc write cycle time 55 ns t aw address valid to end of write 50 ns t cw chip enable to end of write 50 ns t as address setup time 0 ns t wp write pulse width 45 ns t wr write recovery time 0 ns t dw data to write time overlap 25 ns t dh data hold from end of write time 0 ns t ow output active from end of write 5 ns t wz write to output in high-z 20 ns t bw byte enable to end of write 45 ns timing waveform of write cycle no. 1 ( ce controlled)
p4c1041l - low power 256k x 16 static cmos ram page 6 document # sram142 rev or timing w aveform of write cycle no. 2 ( ble or bhe controlled) timing w aveform of write cycle no. 3 ( we controlled, oe low)
p4c1041l - low power 256k x 16 static cmos ram page 7 document # sram142 rev or ac test conditions input pulse levels gnd to 3.0v input rise and fall times 3ns input timing reference level 1.5v output timing reference level 1.5v output load see figures 1 and 2 figure 1. output load figure 2. thevenin equivalent * including scope and test fxture. note: because of the ultra-high speed of the p4c1041l, care must be taken when testing this device; an inadequate setup can cause a normal function - ing part to be rejected as faulty. long high-inductance leads that cause supply bounce must be avoided by bringing the v cc and ground planes directly up to the contactor fngers. a 0.01 f high frequency capacitor is also required between v cc and ground. to avoid signal refections, proper termination must be used; for example, a 50? test environment should be terminated into a 50? load with 1.77v (thevenin voltage) at the comparator input, and a 589? resistor must be used in series with d out to match 639? (thevenin resistance). truth table mode ce oe we ble bhe i/o 0 - i/o 7 i/o 8 - i/o 15 power powerdown h x x x x high z high z standby read all bits l l h l l d out d out active read lower bits only l l h l h d out high z active read upper bits only l l h h l high z d out active write all bits l x l l l d in d in active write lower bits only l x l l h d in high z active write upper bits only l x l h l high z d in active selected, outputs disabled l h h x x high z high z active
p4c1041l - low power 256k x 16 static cmos ram page 8 document # sram142 rev or data rete ntion sym parameter test conditions min max unit v dr vcc for data retention ce v cc - 0.2v, v in v cc - 0.2v or v in 0.2v 2.0 5.5 v i ccdr data retention current v dr =2.0v 30 a t cdr chip deselect to data retention time see retention waveform 0 ns t r operating recovery time t rc ns low v cc data rete ntion waveform
p4c1041l - low power 256k x 16 static cmos ram page 9 document # sram142 rev or ordering in formation
p4c1041l - low power 256k x 16 static cmos ram page 10 document # sram142 rev or tsop ii small outli n e package pkg # t2 # pins 44 symbol min max a 0.039 0.047 a 2 0.033 0.045 b 0.012 0.017 d 0.717 0.733 e 0.0315 bsc e 0.453 0.473 e1 0.392 0.408
p4c1041l - low power 256k x 16 static cmos ram page 11 document # sram142 rev or revisions document number sram 142 document title p4c1041l - low power 256k x 16 static cmos ram rev issue date origin ator description of change or mar-2011 jdb new data sheet

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